The present invention relates to a method of designing package for a semiconductor device, to a layout design tool for performing the same, and to a method of manufacturing a semiconductor device using the same.
In a known package design method for a semiconductor device, it is checked the positions of external connection terminals, such as bumps, connected to predetermined terminals of an LSI and the positions of pins connected to substrate-side terminals electrically connected to the external connection terminals such as the bumps, an examination on a connection method is made, and then a wiring process is performed. In recent years, a wiring process is automated but it is not possible to apply a tool to all wiring lines. Therefore, in order to suppress wiring noises, a design engineer has examined states of respective signal lines and set a wiring path and a wiring line width such that resistance, capacitance, and inductance parasitic on the respective wiring lines are close to each other in a uniform manner.
However, for the purpose of optimization of the resistance, capacitance, and inductance, it is necessary to individually and repeatedly modify the resistance, the capacitance, and the inductance and a modification method uses the know-how based on experience. Accordingly, for new factors or unexpected specifications, noises cannot be completely suppressed, which causes a problem in that the noises due to the new factors or unexpected specifications should be solved by using an externally mounted circuit.
Here, the noise refers to a difference between an ideal waveform and a signal waveform, which occurs due to resistance, capacitance, and inductance parasitic on signal lines, and types of the difference includes overshoot, undershoot, slue, and the like. The slue means a slope of a signal waveform.
FIG. 11 is a flow chart illustrating a package design method in the related art. In FIG. 11, reference numeral 107 denotes a step of determining a wiring path and a wiring line width, reference numeral 102 denotes a layout design step, reference numeral 103 denotes a layout information extracting step, reference numeral 105 denotes a layout modifying step, reference numeral 109 denotes an C·C·R optimization examining step, reference numeral 108 denotes an C·C·R check step, and reference numeral 106 denotes a design completing step.
In a known package design method, first, an examination on wiring lines is made in the step 107 of determining a wiring path and a wiring line width, and then a wiring process is performed in the layout design step 102. At this time, the examination on wiring lines is made on the basis of experience of an engineer.
Then, the resistance, capacitance, and inductance parasitic on the signal lines are extracted in the layout information extracting step 103, and then values thereof are checked in the C·C·R check step 108. Here, L denotes inductance, C denotes capacitance, and R denotes resistance. At this time, if expected values and the extracted values are greatly different from each other, an examination is made such that each of the resistance, capacitance, and inductance can be optimized in the L·C·R optimization examining step 109, and then a wiring line layout is modified according to the examination result in the layout modifying step 105.
Thereafter, the layout design step 102 is performed, then information on parasitic components is extracted in the layout information extracting step 103, and then the values of the resistance, capacitance, and inductance are checked in the L·C·R check step 108. By repeatedly performing the processes described above, each value of a signal line exists within an allowable level in the L·C·R check step 108, thereby realizing a package design by which noises can be suppressed. Patent Document 1 is exemplified below.
[Patent Document 1] JP-A-2001-94014
In a known package design method for a semiconductor device, when wiring signal lines, a design engineer should examine the states of respective signal lines, expect resistance, capacitance, and inductance parasitic on each of the signal lines, and set a wiring path, a wiring line width, a wiring line length such that the parasitic components of the respective signal lines are close to each other in a uniform manner.
However, in the known method, a unit that optimizes the resistance, capacitance, and inductance parasitic on signal lines individually modifies the resistance, capacitance, and inductance. As a result, for example, even if one of the resistance, capacitance, and inductance becomes optimized, the others are not easily optimized. Accordingly, the know-how based on experience is required for the optimization but design engineers having a corresponding technology are limited. This has caused a problem in that process automation due to a tool or the like and the improvement of efficiency of flow due to process simplification are not possible. In addition, since the number of wiring lines required for a package increases every year as the circuit size of an LSI is large, the time required for design also increases due to an increase of the number of layout modification times.
In addition, as the LSI has a high performance, input and output signals need high frequencies. In this case, the layout is not only modified, but a filter serving to remove high-frequency components, which are not needed, is often mounted in the package so as to prevent signal noises.
FIG. 12 is a flow chart illustrating a package design method of designing a package, in which a filter is mounted, in Patent Document 1. In FIG. 12, reference numeral 110 denotes a filter interposing step.
In recent years, it is required that input and output signals also have high frequencies. Accordingly, even if desired values are obtained as values of the resistance, capacitance, and inductance parasitic on wiring lines in the L·C·R check step 108, unexpected noises has often occurred to cause a product to malfunction. In this case, the malfunction due to noises is prevented by modifying the layout by means of optimization of parasitic components and mounting a filter, which removes unnecessary high-frequency components, in a package.
However, since it is necessary to prepare other circuits in the package, additional processes are needed and prices of components increases. In addition, since resistance, capacitance, and inductance due to a mounted filter occur, it may be necessary to modify an error from a desired value. Even in this case, since other processes are added and prices of components increase, a problem occurs.